The present invention relates in general to output driver circuits for providing a high or low voltage at an output terminal and more particularly to output driver circuits having a tristate output mode that electrically isolates the output terminal.
A schematic diagram of an equivalent circuit of one type of a typical prior art tristate driver circuit 10 is shown in FIG. 1. The circuit includes two switches, S1 and S2, that serve to couple the output 12 to a high logic voltage, to a low logic voltage, or to electrically isolate the output 12. Resistors 15 and 18, current source Ibias, and termination voltage source Vterm determine the value of the high logic and low logic voltages that are coupled to the output terminal 12. In a first state, switch S1 is closed and switch S2 is open. Assuming that the value RL of the load resistor 18 is large with respect to the value R1 of resistor 15, the voltage Vout at the output 12 is a high logic voltage VH that is slightly less than the positive power supply voltage, VDD, as long as Vterm is less than VDD. In a second state, switches S1 and S2 are both closed. The voltage Vout at the output 12 is a low logic voltage VL greater than the negative power supply voltage, VSS. The approximate value of VL is equal to VDD-Ibias.times.R1. In a third, high impedance tristate mode, both of the switches S1 and S2 are open to electrically isolate the output terminal 12 from the positive power supply voltage VDD and the negative power supply voltage VSS. The output terminal 12 is coupled only to the termination voltage supply Vterm through load resistor 18. Since the output terminal 12 is electrically isolated from the rest of the driver circuit 10, the voltage Vout at the output terminal 12 is equal to Vterm.
In order that the driver circuit 10 of FIG. 1 switch in a smooth manner (no voltage spikes or "glitches") from either the first or second state to the tristate, both switches S1 and S2 must be opened at precisely the same time. If one switch is opened while the other switch is still closed, the output 12 can temporarily switch from a true (valid) logic state to another false (invalid) logic state before the termination voltage is reached. A temporary false logic state can produce an incorrect output in a subsequent circuit coupled to the output terminal 12. Alternatively, the output terminal 12 can reach a voltage that overstresses the driver circuit 10 or subsequent circuits coupled to the output terminal 12.
As an example, the output of the driver circuit 10 is at VL when switches S1 and S2 are closed. To obtain the high impedance tristate, switches S1 and S2 must be subsequently opened at precisely the same time. If switch S1 opens before S2, current source Ibias pulls Vout negative, creating an undesirable negative going spike that is lower than VL. When switch S2 finally opens, the negative going spike settles out. The output 12 is then electrically isolated from the power supply voltages VDD and VSS and Vout settles to Vterm. Alternatively, if switch S2 opens before S1, resistor 15 pulls Vout toward the positive power supply voltage VDD, creating a temporary false high logic level at the output 12. When switch S1 finally opens, the positive going spike settles out. The output 12 is again electrically isolated from the power supply voltages VDD and VSS and Vout settles to Vterm.
The graph in FIG. 2 illustrates the possible undesirable transitions between the high logic voltage VH, the low logic voltage VL, and the termination voltage Vterm. For purposes of illustrating the behavior of driver circuit 10 only, Vterm is assumed to be halfway between VH and VL. FIG. 2 shows a negative going spike creating a false low logic state from VH to Vterm, a negative going spike overstressing the circuit from Vterm to VL, a positive going spike creating a false logic state from VL to Vterm, and a positive going spike overstressing the circuit from Vterm to VH.
A second type of prior art driver circuit 20 is shown in FIG. 3 having a voltage clamping feature. The mechanism for placing driver circuit 20 into the tristate mode is not shown. The driver circuit 20 includes a buffer stage 22 and an inverter stage 24 having inputs coupled together and to the input voltage, Vi. The outputs of buffer stage 22 and inverter stage 24 are respectively coupled to transistors Q7 and Q8 that are configured as output switches. Transistors Q7 and Q8 are shown as metal-semiconductor field-effect transistors ("MESFETS"), but other types of field-effect ("FETS") transistors are used. Transistors Q7 and Q8 are alternatively switched according to the polarity of the input voltage, Vi. Thus, transistors Q7 and Q8 couple either the high logic voltage VH or the low logic voltage VL to the output terminal 12.
In the prior art driver circuit 20 of FIG. 3, the switching waveforms at the output of buffer stage 22 and inverter stage 24 should ideally be precisely complementary. If this is not the case, the output waveform Vout, shown in FIG. 4, can exhibit undesirable multiple slopes or "kinks" when switched from the high logic level VH to the low logic level VL.
Also in prior art driver circuit 20 of FIG. 3, a voltage clamp is typically used to clamp the gates of transistors Q7 and Q8 (nodes 14 and 16) to a negative fixed potential in the tristate mode to ensure that transistors Q7 and Q8 are off and the value of nodes 14 and 16 is set to a predetermined value. The voltage clamp includes diodes 11 and 12 and the fixed potential Vbias. As mentioned above, FETs are typically used for the output switching transistors Q7 and Q8. Since FETs are symmetrical devices, the drain and source of the device are determined by the applied voltage and therefore the drain and source can become exchanged. Thus, the problem with a fixed potential clamp is that the clamp may not limit current for all values of the termination voltage, Vterm. For example, if it is assumed that VL=0 volts, Vbias=-3 volts, Vterm is greater than 0 volts, and transistor Q8 is a normally on depletion FET with a pinch-off voltage, Vp, of -0.7 volts, then transistor Q8 is off. However, if Vterm becomes more negative than Vbias, the drain and source of transistor Q8 reverse, and the clamp voltage Vbias does not turn off transistor Q8, but rather allows transistor Q8 to conduct current from VL to Vterm.
A third type of prior art tristate driver circuit (not shown) has a series-connected switch at the output terminal that is opened when the tristate mode is desired. Placing an additional switch in series with the output undesirably increases the output impedance of the driver circuit in a manner that is poorly controlled due to the variability of the series resistance of FET switching elements. Additionally, bias current flowing through the series-connected switch can create an excess voltage drop across circuit elements such as the load resistor.
What is desired is a tristate output driver circuit that does not have undesirable glitches or multiple slopes in the output, remains in the tristate mode for a broad range of the termination voltage, and does not require a series-connected output switch.